For the layout of electronic components, e.g., of semiconductor components, power semiconductor chips and logic chips may be embodied as separate chips, because the corresponding semiconductor processes may be optimized individually for both functionalities (functionalities oriented to power semiconductor chips or logic chips).
However, at least one logic chip and at least one power semiconductor chip are typically combined in electronic assemblies in order to execute a specific circuit function.
It is therefore economical for both types of chip, i.e., power semiconductor chips and logic chips, to be able to be integrated as one functional unit in a compact housing and/or in a compact package in order to reduce an overall size and outlay in the use of the electronic assemblies made of logic chips and power semiconductor chips. In this case, the compact housing and/or the compact package is used as protection for the electronic assemblies contained therein from the environmental conditions in an application, but electrical and thermal contacts of the power semiconductor chip and/or the logic chip to one another and to a base plate must be implemented.
In this case, high power losses occur in power semiconductor chips, which must be dissipated via the back of the power semiconductor chip to the environment and/or to a thermally conductive base plate, for example, so that overheating of the power semiconductor chip is avoided.
Typically, power semiconductor chips are soldered onto one side of a base plate, normally made of metal, the base plate being implemented with one or more terminal units in order to electrically couple the power semiconductor chip to external circuit units via its back. Further connection terminals of the power semiconductor chip are provided with metallic contact lugs via further terminal units and led to the outside. After embedding the electronic assembly using a molding compound (e.g., plastic cast and/or plastic casting compound), the terminal units of the power semiconductor chip and the terminal units of the base plate are freely accessible, i.e., the corresponding terminal units are not coated with plastic.
If logic chips are to be positioned together with power semiconductor chips in a single package, other systems provide that the metallic base plate conducts at least one electrical potential of at least one power semiconductor chip; in this case potential differences and/or voltages of several hundred volts may arise, which may impair the functionality of logic chips and/or may even completely destroy the logic chip.
Furthermore, these voltages may exhibit strong transient oscillations, which leads to the logic chips having to resist high transient voltages. This requires complex shielding measures on the logic chip.
The semiconductor process used to produce a logic chip must also be configured for high blocking voltages, which is not expedient.
A method which attempts to avoid this problem is discussed in German Published Patent Application No. 197 16 674. In this case, the circuit modules packed in the housing (logic chips and power semiconductor chips) are distributed onto multiple base plates which are electrically insulated from one another, whereby it is possible to keep high voltages and/or potential differences away from the sensitive logic chips. The above-mentioned method provides that multiple base plates which are electrically insulated from one another must be positioned next to one another in the housing, so that for a predetermined area, only a smaller total component area may be packed than if only one (electrically conductive, metallic) base plate is provided, since the circuit modules must have a sufficient insulation distance from one another and from the edge of a base plate.
A further method and a device for packaging circuit modules is discussed in PCIM 200, Conference Proceedings, PC7.2, “Power Semiconductor Packaging—Problem or resource?, From the state of the art to future trends”, a metal-plated ceramic base plate being used instead of a metallic base plate in this case.
Through targeted structuring of the metal plating on the base plate, electrical isolation of the backs of power and/or logic chips may be achieved. This method and this device provide that a ceramic reduces the thermal conductivity of the package, making heat dissipation from the circuit modules more difficult. The above-mentioned method provides for complex manufacturing of the ceramic, due to which the module package is associated with higher costs than a module package which is based on a single metallic base plate.
It is therefore an object of the present invention to provide a method for packaging circuit modules and a multiple chip package, at least one logic chip and at least one power semiconductor chip being combined on a uniform metallic base plate in a multiple chip package.